1. Field of the Invention
The present invention relates to an apparatus and a method for increasing semiconductor device density. In particular, the present invention relates to a stacked multi-substrate device using a combination of flip-chips and chip-on-board assembly techniques to achieve densely packaged semiconductor devices.
2. State of the Art
Chip-On-Board techniques are used to attach semiconductor dice to a printed circuit board, including flip-chip attachment, wirebonding, and tape automated bonding (“TAB”). Flip-chip attachment consists of attaching a flip-chip to a printed circuit board or other substrate. A flip-chip is a semiconductor chip that has a pattern or array of electrical terminations or bond pads spaced around an active surface of the flip-chip for face down mounting of the flip-chip to a substrate. Generally, the flip-chip has an active surface having one of the following electrical connectors: Ball Grid Array (“BGA”), an array of minute solder balls is disposed on the surface of a flip-chip that attaches to the substrate (“the attachment surface”); Slightly Larger than Integrated Circuit Carrier (“SLICC”), is similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA; or a Pin Grid Array (“PGA”), wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip-chip . The pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto. With the BGA or SLICC, the solder or other conductive ball arrangement on the flip-chip must be a mirror-image of the connecting bond pads on the printed Circuit board such that precise connection is made. The flip-chip is bonded to the printed circuit board by refluxing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip-chip must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the flip-chip is generally bonded by soldering the pins into place. An under-fill encapsulant is generally disposed between the flip chip and the printed circuit board for environmental protection and to enhance the attachment of the flip-chip to the printed circuit board. A variation of the pin-in-recess PGA is a J-lead PGA, wherein the loops of the J's are soldered to pads on the surface of the circuit board.
Wirebonding and TAB attachment generally begin with attaching a semiconductor chip to the surface of a printed circuit board with an appropriate adhesive, such as an epoxy. In wirebonding, bond wires are attached, one at a time, to each bond pad on the semiconductor chip and extend to a corresponding lead or trace end on the printed circuit board. The bond wires are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bonding, using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding, using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. The semiconductor chip may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding, although face up orientation is more common. With TAB, ends of metal leads carried on an insulating tape, such as a polyamide, are respectively attached to the bond pads on the semiconductor chip and to the lead or trace ends on the printed circuit board. An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As new generations of integrated circuit products are released, the number of devices used to fabricate them tends to decrease due to advances in technology even though the functionality of these products increases. For example, on the average, there is approximately a 10 percent decrease in components for every product generation over the previous generation with equivalent functionality.
In integrated circuit packaging, in addition to component reduction, surface mount technology has demonstrated an increase in semiconductor chip density on a single substrate or board despite the reduction of the number of components. This results in more compact designs and form factors and a significant increase in integrated circuit density. However, greater integrated circuit density is primarily limited by the space or “real estate” available for mounting dice on a substrate, such as a printed circuit board.
One method of further increasing integrated circuit density is to stack semiconductor dice vertically. U.S. Pat. No. 5,012,323, issued Apr. 30, 1991 to Farnworth, teaches combining a pair of dice mounted on opposing sides of a lead frame. An upper, smaller die is back-bonded to the upper surface of the leads of the lead frame via a first adhesively coated, insulated film layer. A lower, larger die is face-bonded to the lower lead frame die-bonding region via a second, adhesively coated, insulative film layer. The wirebonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum bond wires. The lower die must be slightly larger than the upper die such that the die pads are accessible from above through a bonding window in the lead frame such that gold wire connections can be made to the lead extensions. This arrangement has a major disadvantage from a production standpoint as the same size die cannot be used.
U.S. Pat. No. 5,291,061, issued Mar. 1, 1994 to Ball (“Ball”), teaches a multiple stacked dice device containing up to four stacked dice supported on a die-attach paddle of a lead frame, the assembly not exceeding the height of current single die packages, and wherein the bond pads of each die are wirebonded to lead fingers. The low profile of the device is achieved by close-tolerance stacking which is made possible by a low-loop-profile wirebonding operation and thin adhesive layers between the stacked dice. However, Ball requires long bond wires to electrically connect the stacked dice to the lead frame. These long bond wires increase resistance and may result in bond wire sweep during encapsulation. Also, Ball requires the use of spacers between the dice.
U.S. Pat. No. 5,323,060, issued Jun. 21, 1994 to Fogal et al. (“Fogal”), teaches a multi-chip module that contains stacked die devices, the terminals or bond pads of which are wirebonded to a substrate or to adjacent die devices. However, as discussed with Ball, Fogal requires long bond wires to electrically connect the stacked die bond pads to the substrate. Fogal also requires the use of spacers between the dice.
U.S. Pat. Nos. 5,422,435 and 5,495,398 to Takiar et al. (“Takiar”), teach stacked dice having bond wires extending to each other and to the leads of a carrier member such as a lead frame. However, Takiar also has the problem of long bond wires, as well as, requiring specific sized or custom designed dice to achieve a properly stacked combination.
U.S. Pat. No. 5,434,745, issued Jul. 18, 1995 to Shokrgozar et al. (“Shokrgozar”), discloses a stackable packaging module comprising a standard die attached to a substrate with a spacer frame placed on the substrate to surround the die. The substrate/die/spacer combinations are stacked one atop another to form a stacked assembly. The outer edge of the spacer frame has grooves in which a conductive epoxy is disposed. The conductive epoxy forms electric communication between the stacked layers and/or to the final substrate to which the stacked assembly is attached. However, Shokrgozar requires specialized spacer frames and a substantial number of assembly steps, both of which increase the cost of the final assembly.
U.S. Pat. No. 5,128,831, issued Jul. 7, 1992 to Fox, III et al. (“Fox”), also teaches a standard die attached to a substrate with a spacer frame placed on the substrate to surround the die. The stacked layers and/or the final substrate are in electric communication with conductive vias extending through the spacer frames. However, Fox also requires specialized spacer frames, numerous assembly steps, and is limited in its flexibility to utilize a variety of dice.
U.S. Pat. No. 5,513,076, issued Apr. 30, 1996 to Werther (“Werther”), teaches the use of interconnecting assemblies to connect integrated circuits in an integrated manner.
As has been illustrated, none of the cited prior art above uses or teaches flip-chip manufacturing methods for attaching dice together in a stacked manner to form a stacked die assembly.
Therefore, it would be advantageous to develop a stacking technique and assembly for increasing integrated circuit density using a variety of non-customized die configurations in combination with commercially available, widely-practiced semiconductor device fabrication techniques.